This disclosure relates generally to the field of integrated circuit manufacturing, and more particularly to verification patterns for optical proximity correction (OPC) numerical models.
The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography or lithography. Lithographic processes can be used to transfer a pattern of a photomask (or mask) to a semiconductor wafer.
A pattern may be formed using a photoresist layer disposed on a wafer by passing light energy through a photomask (or mask) of the pattern to image the desired pattern onto the photoresist layer. The pattern is thereby transferred to the photoresist layer. In areas where the photoresist is sufficiently exposed to the light, and after a development process, the photoresist material becomes soluble such that it may be removed to selectively expose an underlying layer (e.g., a semiconductor layer, hard mask layer, etc.). Portions of the photoresist layer not exposed to a threshold amount of light energy will not be removed and serve to protect the underlying layer during further processing of the wafer (e.g., etching exposed portions of the underlying layer, implanting ions into the wafer, etc.). After processing is completed, the remaining portions of the photoresist layer may be removed.
There is a trend in IC fabrication to increase the density with which various structures are arranged on a wafer; feature size, line width, and the separation between features and lines are becoming increasingly smaller. For example, nodes with a critical dimension (CD) of about 65 nanometers (nm) to about 45 nm have been proposed. In these sub-micron processes, yield of the wafer manufacturing process is affected by factors such as mask pattern fidelity, optical proximity effects, and photoresist processing. Some of the more prevalent concerns include line end pullback or bridging, corner rounding, and line width variations. Contact holes may also have a tendency to bridge and/or shift from a desired location. These concerns are largely dependent on local pattern density and topology.
OPC modeling is a technique used to improve lithographic image fidelity in semiconductor fabrication. OPC involves executing an OPC software program on a computer. The OPC program carries out a computer simulation that takes an initial data set having information relating to a desired pattern on a semiconductor product, and manipulates the data set to arrive at a corrected data set in an attempt to compensate for the above-mentioned concerns. The photomask can then be made in accordance with the corrected data set. The OPC process can be governed by a set of optical rules, employing fixed rules for geometric manipulation of the data set, modeling principles, employing predetermined behavior data to drive geometric manipulation of the data set, or a hybrid set of optical and fixed rules.
Prior to correcting a data set using OPC, it may be desirable to verify the performance (or accuracy) of the OPC model upon which the OPC routine relies and to select one of a plurality of OPC models to be used during the OPC routine. Verifying an OPC model may involve hand checking layout corrections made to a test pattern that is exposed and printed on a test wafer to verify that the OPC model performs in an expected manner. Such techniques for validating OPC models involve intensively manual processes that are time consuming and prone to error.